1. Field of the Invention
This invention relates generally to semiconductor manufacturing, and more particularly, to a method and apparatus detecting a potential impasse in a process flow and providing a resolution to reduce an interruption resulting from the impasse.
2. Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today's manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital and, therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Generally, a set of processing steps is performed across a group of semiconductor wafers, sometimes referred to as a lot. For example, a process layer that may be composed of a variety of different materials may be formed across a semiconductor wafer. Thereafter, a patterned layer of photoresist may be formed across the process layer using known photolithography techniques. Typically, an etch process is then performed across the process layer using a patterned layer of photoresist as a mask. This etching process results in the formation of various features or objects in the process layer. Such features may be used as, for example, a gate electrode structure for transistors. Many times, trench isolation structures are also formed across the substrate of the semiconductor wafer to isolate electrical areas across a semiconductor wafer. One example of an isolation structure that can be used is a shallow trench isolation (STI) structure.
The manufacturing tools within a semiconductor manufacturing facility typically communicate with a manufacturing framework or a network of processing modules. Each manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface to which a manufacturing network is connected, thereby facilitating communications between the manufacturing tool and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates a control script, which can be a software program that automatically retrieves the data needed to execute a manufacturing process.
FIG. 1 illustrates a typical semiconductor wafer 105. The semiconductor wafer 105 typically includes a plurality of individual semiconductor die 103 arranged in a grid 150. Using known photolithography processes and equipment, a patterned layer of photoresist may be formed across one or more process layers that are to be patterned. As part of the photolithography process, an exposure process is typically performed by a stepper on single or multiple die 103 locations at a time, depending on the specific photomask employed. The patterned photoresist layer can be used as a mask during etching processes, wet or dry, performed on the underlying layer or layers of material, e.g., a layer of polysilicon, metal or insulating material, to transfer the desired pattern to the underlying layer. The patterned layer of photoresist is comprised of a plurality of features, e.g., line-type features or opening-type features that are to be replicated in an underlying process layer.
Turning now to FIG. 2, a flowchart depiction of an illustrative prior art process flow is depicted. A manufacturing system processes one or more wafers from a lot (block 210). A process flow may be created by the manufacturing system, wherein several lots of wafers are stepped through various tools in a fabrication facility (fab). Based upon the processing of wafers, the manufacturing system may detect fault conditions in the process flow (block 220). Based upon the fault conditions within the manufacturing system, the process flow is generally interrupted by an operator in order to address any potential manufacturing problems (block 230). Upon interruption of the process flow, the operator may initiate specific corrective action to address the fault conditions in the process flow (block 240). Based upon the intervening process(es) initiated by the operator, various corrective actions may be implemented, such as manually initiating rerouting of specific lots of wafers, manually moving process materials to alternative portions of the manufacturing system, etc.
One of the problems associated with the current methodology of addressing fault conditions includes the fact that significant disruption of the process flow may occur. This introduces inefficiencies in semiconductor wafer processing. Having to address faults through intervention by an operator may cause delays when determining the type(s) of corrective actions to take and implementing them.
Further, state-of-the-art flow of materials throughout a processing system generally requires intervention by an operator to accommodate process flow alterations. Generally, when wafers are rerouted and/or process tasks are rescheduled, changes relating to delivery of various process materials to a number of regions of a fab must be addressed. Therefore, a fault condition in a process flow that is addressed by an operator (e.g., rerouting various wafers lots) may cause a material load imbalance throughout the system. In other words, certain portions of the system may be inadvertently left with inadequate amounts of process materials, or alternatively, with excessive amounts of process materials as a result of process flow alterations. Additionally, manually addressing faults by performing manual rerouting and rescheduling may result in significant inefficiencies and delays in the process flow. These delays may cause appreciable expense and delay in delivery of finished semiconductor products.
The present invention is directed to overcoming, or at least reducing, the effects of one or more of the problems set forth above.